The so-called “totem pole” output stage consisting of a PMOS transistor as the pull-up transistor in series with a NMOS transistor as the pull-down transistor is well known in the art. In many processes in which integrated circuits having this output stage are fabricated, the PMOS transistor has poorer characteristics than the NMOS transistor. Circuit variations to improve the characteristics of this type of output stage are also well known. One such variation is to place a diode in parallel with the PMOS transistor, the diode being conductive when power is applied to it to provide extra boost when the output voltage is low and to gradually turn OFF as the output voltage rises. Another known technique is to use a transistor in parallel with the output transistor, the additional transistor having its gate tied to a buffer which has its input connected to the output voltage. When the output voltage is low, the transistor is driven ON to provide the extra boost to the output circuit and when the output voltage rises to the level at which the inverter switches, the additional transistor is turned OFF. Both of these techniques provide additional output drive abilities during the switching transient but not during the steady state output.
FIG. 1 shows an output waveform for a circuit that has both the additional diode in parallel with the output transistor and the additional transistor in parallel with the output transistor driven by the inverter described above. The load is a transmission line with a characteristic impedance of 65 ohms and a length of 10 centimeters. As can be seen from the waveforms in FIG. 1, the circuit not only exhibits overshoot and undershoot, but exhibits strong noise components both in the high and low portions of the waveform. These noise transitions are probably due to the switching of the additional transistor. In FIG. 1 the nominal curve shows a typical process in the fabrication of the transistors and a typical supply voltage. The strong waveform shows the best process producing transistors having the highest gain and the highest supply voltage. A strong waveform is shown at both −40 degrees Centigrade and +85 degrees Centigrade, the temperature range at which the circuit must operate. The weak waveforms shows the worst case process producing transistors having the lowest gain and the lowest supply voltage. A weak waveform is also shown at −40 degrees Centigrade and +85 degrees Centigrade.
A major problem facing the electronic industry today is its trade-off between speed and noise. As a flow of data on memory busses continues to increase in frequency, the problem of EMI and other noise issues has grown as well. Memory drivers are required to drive high data rates that has caused output edge rates to decrease, especially at low voltages utilizes with advanced process technology. This, in turn, results in higher electromagnetic interference (EMI) and signal noise to cause the receiver to detect false data. Additionally, as voltages drop below 2 volts, and transistor gate thickness is reduced, receivers are more susceptible to damage from overshoots and undershoots. Accordingly, there is a need for an output stage which has reduced propagation delay while maintaining good signal integrity, that is minimizing overshoot and undershoot. In addition, there is a need for such stage which generates a minimum EMI.